opensta

Parallax Static Timing Analyzer

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  1. Package version
    opensta-2.2.0p0
  2. Maintainer
    Alessandro De Laurenzis

OpenSTA is a gate level static timing verifier. As a stand-alone
executable it can be used to verify the timing of a design using
standard file formats:
- Verilog netlist
- Liberty library
- SDC timing constraints
- SDF delay annotation
- SPEF parasitics

OpenSTA uses a TCL command interpreter to read the design, specify
timing constraints and print timing reports.

  • devel/bison
  • devel/swig
  • tcl->=8.6,<8.7:lang/tcl/8.6
  • devel/cmake
  • devel/ninja