qflow

full end-to-end digital synthesis flow for VLSI ASIC designs

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  1. Package version
    qflow-1.4.83p1
  2. Maintainer
    Alessandro De Laurenzis

A digital synthesis flow is a set of tools and methods used to turn a
VLSI design written in a high-level behavioral language like Verilog
or VHDL into a physical circuit, which can either be configuration code
for an FPGA target or a layout in a specific technology, that would
become part of an IC.
Qflow uses a complete and open source tool chain for synthesizing
digital circuits starting from Verilog source and ending in physical
layout for a specific target fabrication process.

  • tcl->=8.5,<8.6:lang/tcl/8.5
  • cad/yosys
  • cad/graywolf
  • cad/opensta
  • cad/qrouter
  • cad/magic
  • cad/netgen
  • lang/python/3.10
  • devel/gmake

  • tcl->=8.5,<8.6:lang/tcl/8.5
  • cad/yosys
  • cad/graywolf
  • cad/opensta
  • cad/qrouter
  • cad/magic
  • cad/netgen
  • lang/python/3.10,-tkinter
  • shells/tcsh
  • sysutils/ggrep
  • lang/python/3.10